Design Low Power 130mW Pipeline ADC With Speed 80 MSPS 8-bit
نویسندگان
چکیده
This paper describes a pipeline analog-to-digital converter is implemented for high speed camera. In the pipeline ADC design, prime factor is designing operational amplifier with high gain so ADC have been high speed. The other advantage of pipeline is simple on concept, easy to implement in layout and have flexibility to increase speed. We made design and simulation using Mentor Graphics Software with 0.35 m CMOS technology with a total power dissipation of 130 mW. Circuit techniques used include a precise comparator with latch, operational amplifier and Non-Overlapping clock. A switched capacitor is used to sample, multiplying and hold at each stage. Simulation a worst case DNL and INL of 0,6 LSB. The design operates at 3,3 V dc. The speed camera cmos at 10.000 frames/s.
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